The present invention relates to a power supply control circuit which is preferably used for controlling a power supply voltage for a class-G amplifier.
An amplifier consumes an electric power which is equal to the product of a load current which flows through a load, and a difference between a power supply voltage given to the amplifier and an output voltage which is supplied from the amplifier to the load. In order to reduce the power consumption of a whole apparatus including an amplifier and a load, the power consumption which is caused in the amplifier itself must be suppressed as low as possible. As an amplifier which satisfies such a request, a class-G amplifier is known in which a power supply voltage for an amplification operation is switched in accordance with the amplitude of an input signal or an output signal (for example, see JP-A-2000-223966).
FIG. 5 is a circuit diagram showing an example of the configuration of a class-G amplifier of this kind. In the example, the class-G amplifier has an amplifying section 1, a charge pump 2, and a power supply control circuit 3. Here, the amplifying section 1 is a power amplifier such as a headphone amplifier, and amplifies an input voltage VIN to generate an output voltage VOUT for driving a load 1A such as a speaker. The charge pump 2 is a power supply which boosts a predetermined power supply voltage to generate a positive power supply voltage +VB and a negative power supply voltage −VB, and which supplies the voltages to the amplifying section 1. The boost mode of the charge pump 2 includes a middle power mode where positive and negative power supply voltages +VDD, −VDD of a predetermined magnitude are generated as the positive and negative power supply voltages +VB, −VB, and a low power mode where positive and negative power supply voltages +VDD/2, −VDD/2 of a magnitude which is a half of that in the middle power mode. The power supply control circuit 3 monitors the output voltage VOUT of the amplifying section 1, and the positive and negative power supply voltages +VB, −VB for the amplifying section 1, and, based on a result of the monitoring, executes a mode up in which the boost mode of the charge pump 2 is switched from the low power mode to the middle power mode, or a mode down in which the boost mode is switched from the middle power mode to the low power mode.
The power supply control circuit 3 will be described in further detail. In a state where the charge pump 2 operates in the low power mode, when the peak value of the output voltage VOUT of the amplifying section 1 and the positive and negative power supply voltages +VB, −VB approach each other with exceeding a predetermined limit value, the power supply control circuit 3 changes the mode of the charge pump 2 from the low power mode to the middle power mode (the mode up), in order to prevent waveform distortion from occurring in the output voltage VOUT. In a state where the charge pump 2 operates in the middle power mode, when the state where the absolute value of the output voltage VOUT of the amplifying section 1 is lower than a predetermined threshold voltage continues for a predetermined time period or longer, the power supply control circuit 3 changes the mode of the charge pump 2 from the middle power mode to the low power mode (the mode down), in order to reduce the power consumption of the amplifying section 1 itself. As described above, the magnitudes of the positive and negative power supply voltages +VB, −VB which are supplied from the charge pump 2 to the amplifying section 1 are switched in accordance with the magnitude of the output voltage VOUT of the amplifying section 1. Therefore, the power consumption of the amplifying section 1 itself can be reduced while preventing waveform distortion from occurring in the output voltage VOUT of the amplifying section 1.
In the above-described related class-G amplifier, in the case where conditions for the mode down are loose, specifically, in the case where, when the mode down is to be performed under conditions that the state where the absolute value of the output voltage VOUT is smaller than the predetermined threshold voltage continues for the predetermined time period or longer, the threshold voltage is high, the mode down is easily performed after the mode up, and a phenomenon in which the mode up and the mode down are alternately repeated occurs. When such mode switching occurs frequently, noises are frequently produced in the output voltage VOUT of the amplifying section 1. In the related technique, while considering production dispersions among elements constituting the class-G amplifier, the range of the load current of the load 1A, and the like, therefore, conditions for the mode down are sufficiently strictly set so that the above-described frequent mode switching does not occur even under the worst conditions. That means, the threshold voltage is low when the mode down is to be performed under conditions that the state where the absolute value of the output voltage VOUT is smaller than the predetermined threshold voltage continues for the predetermined time period or longer. Because of the strict conditions for the mode down, however, there arises the following problem. Despite of the state where the absolute value of the output voltage VOUT of the amplifying section 1 is reduced in the middle power mode, and the switching to the low power mode is not problematic, the mode down is not performed for a long time period, thereby causing a problem in that waste power consumption occurs.